Features
• Ultra low-voltage core and I/O power supplies
– VDD2 = 1.14–1.30V
– VDDCA/VDDQ = 1.14–1.30V
– VDD1 = 1.70–1.95V
• Clock frequency range
– 533–10 MHz (data rate range: 1066–20 Mb/s/pin)
• Four-bit prefetch DDR architecture
• Eight internal banks for concurrent operation
• Multiplexed, double data rate, command/address
inputs; commands entered on every CK edge
• Bidirectional/differential data strobe per byte of
data (DQS/DQS#)
• Programmable READ and WRITE latencies (RL/WL)
• Programmable burst lengths: 4, 8, or 16
• Per-bank refresh for concurrent operation
• On-chip temperature sensor to control self refresh
rate
• Partial-array self refresh (PASR)
• Deep power-down mode (DPD)
• Selectable output drive strength (DS)
• Clock stop capability
• RoHS-compliant, “green” packaging
Options Marking
• VDD2: 1.2V L
• Configuration
– 32 Meg x 16 x 8 banks x 1 die 256M16
– 16 Meg x 32 x 8 banks x 1 die 128M32
– 16 Meg x 32 x 8 banks x 2 die 256M32
– 1 (16 Meg x 32 x 8 banks) + 2 (32
Meg x 16 x 8 banks)
384M32
– 32 Meg x 16 x 8 banks x 4 die 512M32
– 16 Meg x 32 x 8 banks x 2 die 128M64
– 16 Meg x 32 x 8 banks x 3 die 192M64
– 16 Meg x 32 x 8 banks x 4 die 256M64
• Device type
– LPDDR2-S4, 1 die in package D1
– LPDDR2-S4, 2 die in package D2
– LPDDR2-S4, 3 die in package D3
– LPDDR2-S4, 4 die in package D4
• FBGA “green” package
– 134-ball FBGA (10mm x
11.5mm)
GU, GV
– 168-ball FBGA (12mm x 12mm) LF, LG
– 216-ball FBGA (12mm x 12mm) LH, LK, LL, LM,
LP
– 220-ball FBGA (14mm x 14mm) LD, MP
– 240-ball FBGA (14mm x 14mm) MC
– 253-ball FBGA (11mm x 11mm) EU, EV
• Timing – cycle time
– 1.875ns @ RL = 8 -18
– 2.5ns @ RL = 6 -25
– 3.0ns @ RL = 5 -3
• Operating temperature range
– From –30°C to +85°C WT
– From –40°C to +105°C AT
